Although it requires a new generation of test equipment, testing MEMS devices is challenging but not impossible. Since the early days of the IC industry, wafer-level test has been possible using ...
A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...
Wafer inspection has become a critical part of the semiconductor manufacturing process. Inspections performed after wafer test can analyze the marks left by probe cards to ensure that the test process ...
Aehr Test Systems, Inc. (NASDAQ:AEHR) draws focus as orders for wafer-level burn-in equipment tied to AI processors and ...
STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announced the successful production of the world’s first semiconductor wafer whose ...
Increased productivity and efficiency with one-pass test enabled by a high-voltage switching matrix Designed to enhance the safety of operators and equipment; complies with regulations SANTA ROSA, ...
FREMONT, CA / ACCESSWIRE / January 7, 2025 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has received an initial production ...
FREMONT, CA / ACCESSWIRE / December 14, 2023 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has received an initial customer ...
The use of on-wafer superconducting materials, other novel materials, and traditional semiconductors at cryogenic temperatures (below about 123K, or -150°C) has grown quickly in recent years.
Suppliers of probe cards, test sockets, and other IC test interface solutions are gearing up for a boom in 3nm chip demand in 2024 and 2025. IC test and verification labs are gearing up for a ramp-up ...
High testing parallelism can be achieved with contactless wafer testing, which leads to reduced production cycle times. It also eliminates the possibility of wafer damage during testing. According to ...
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